This invention relates to semiconductor devices and methods of manufacture, and more particularly to field effect transistors formed wholly within overlying layers of polycrystalline silicon on a face of an integrated circuit chip.
In U.S. Pat. No. 3,519,901, issued July 7, 1970 to Bean and Martin, assigned to Texas Instruments, circuit elements formed in polycrystalline silicon layers on a face of a silicon integrated circuit chip are disclosed. Using this concept, component densities may be increased because devices may overly one another. An example of use of the concept is disclosed in U.S. Pat. No. 4,110,776 to G. R. Mohan Rao et al, assigned to Texas Instruments, where an N-channel static MOS RAM cell is shown using polycrystalline silicon load resistors. Other examples are the static memory cells disclosed in U.S. Patents of D. J. McElroy, U.S. Pat. No. 4,092,735 and 4,142,111, both assigned to Texas Instruments, where resistors in polycrystalline silicon layers are used.
In static RAM cells, several design compromises need be made involving the power dissipation, speed of operation, cell size or density, yield, and the like. In each cell of the bistable type, one side is always conductive and the other cut off. To limit the current through the conductive side and thus minimize power dissipation, the load device should be of a high impedance, but this is inconsistent with high speed switching.
It is the primary object of this invention to provide an improved load device for a static RAM cell in an MOS integrated circuit. Another object is to provide a field-effect transistor element formed wholly within polycrystalline silicon layers. An additional object is to provide resistor elements which may be switched in impedance and are compatible in manufacture with N-channel silicon-gate double level poly MOS integrated circuit.